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| IS61SF12832 IS61SF12836 128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES * Fast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns, and 12 ns * Internal self-timed write cycle * Individual Byte Write Control and Global Write * Clock controlled, registered address, data inputs and control signals * PentiumTM or linear burst sequence control using MODE input * Three chip enables for simple depth expansion and address pipelining * Common data inputs and data outputs * JEDEC 100-Pin TQFP and 119-pin PBGA package * Single +3.3V +10%, -5% power supply * Power-down snooze mode ISSI (R) APRIL 2001 DESCRIPTION The ISSI IS61SF12832 and IS61SF12836 are high-speed synchronous static RAM designed to provide a burstable, high-performance memory for high speed networking and communication applications. It is organized as 131,072 words by 32 bits or 36 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency 7.5 7.5 8.5 117 8 8 10 100 8.5 8.5 11 90 10 10 15 66 12 12 15 66 Units ns ns MHz ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2001, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 1 IS61SF12832 IS61SF12836 BLOCK DIAGRAM MODE Q0 A0' ISSI CLK A0 (R) CLK BINARY COUNTER ADV ADSC ADSP CE CLR Q1 A1' A1 128K x 32, 128K x 36 MEMORY ARRAY 15 17 A16-A0 17 D Q ADDRESS REGISTER CE CLK 32 or 36 32 or 36 GW BWE BW4 DQd BYTE WRITE REGISTERS CLK D Q BW3 D DQc Q BYTE WRITE REGISTERS CLK BW2 DQb BYTE WRITE REGISTERS CLK D Q BW1 D DQa Q BYTE WRITE REGISTERS CLK CE CE2 CE2 D Q 4 ENABLE REGISTER CE CLK INPUT REGISTERS CLK OE 32 or 36 DQ[31:0] or DQ[35:0] D Q ENABLE DELAY REGISTER CLK OE 2 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 IS61SF12832 IS61SF12836 PIN CONFIGURATION 119-pin PBGA (Top View) 1 A VCCQ B NC C NC D DQc1 E DQc2 F VCCQ G DQc5 H DQc7 J VCCQ K DQd1 L DQd4 M VCCQ N DQd6 P DQd8 R NC T NC U VCCQ NC NC NC NC NC VCCQ NC A10 A11 A14 NC ZZ A5 MODE VCC GND A13 NC NC GND A0 GND NC DQa1 DQd7 GND A1 GND DQa3 DQa2 DQd5 GND DQd3 DQd2 GND BW4 CLK NC BWE GND BW1 GND DQa7 DQa5 DQa4 DQa8 DQa6 VCCQ VCC NC VCC NC VCC VCCQ DQc8 GND DQc6 DQc4 GND BW3 DQc3 GND NC GND NC CE OE ADV GW GND GND GND BW2 GND NC DQb6 DQb5 DQb4 DQb2 DQb8 DQb7 VCCQ DQb3 DQb1 A7 A2 VCC A12 A15 NC CE2 A3 A6 A4 2 3 4 5 6 7 ISSI 100-Pin TQFP A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9 (R) ADSP ADSC A8 A9 A16 CE2 VCCQ NC NC DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 NC VCC NC GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 NC 128K x 32 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable ZZ GW OE DQa-DQd MODE VCC GND VCCQ Synchronous Global Write Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V Snooze Enable CE, CE2, CE2 Synchronous Chip Enable A2-A16 CLK ADSP ADSC ADV BW1-BW4 BWE Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16 3 IS61SF12832 IS61SF12836 PIN CONFIGURATION 119-pin PBGA (Top View) 1 A VCCQ B NC C NC D DQc1 E DQc2 F VCCQ G DQc5 H DQc7 J VCCQ K DQd1 L DQd4 M VCCQ N DQd6 P DQd8 R NC T NC U VCCQ NC NC NC NC NC VCCQ NC A10 A11 A14 NC ZZ A5 MODE VCC GND A13 NC DQPd GND A0 GND DQPa DQa1 DQd7 GND A1 GND DQa3 DQa2 DQd5 GND DQd3 DQd2 GND BW4 CLK NC BWE GND BW1 GND DQa7 DQa5 DQa4 DQa8 DQa6 VCCQ VCC NC VCC NC VCC VCCQ DQc8 GND DQc6 DQc4 GND BW3 DQc3 GND DQPc GND NC CE OE ADV GW GND GND GND BW2 GND DQPb DQb6 DQb5 DQb4 DQb2 DQb8 DQb7 VCCQ DQb3 DQb1 A7 A2 VCC A12 A15 NC CE2 A3 A6 A4 2 3 4 5 6 7 ISSI 100-Pin TQFP A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9 (R) ADSP ADSC A8 A9 A16 CE2 VCCQ NC DQPc DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 NC VCC NC GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPb DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 DQPa 128K x 36 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable ZZ DQPa-DQPd GW OE DQa-DQd MODE VCC GND VCCQ Synchronous Global Write Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V Snooze Enable Parity Data I/O CE, CE2, CE2 Synchronous Chip Enable A2-A16 CLK ADSP ADSC ADV BW1-BW4 BWE 4 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16 IS61SF12832 IS61SF12836 TRUTH TABLE Operation Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used CE None None None None None External External External Next Next Next Next Next Next Current Current Current Current Current Current H L L X X L L L X X H H X H X X H H X H CE2 X X L X L H H H X X X X X X X X X X X X CE2 X H X H X L L L X X X X X X X X X X X X ADSP X L L H H L H H H H X X H X H H X X H X ADSC L X X L L X L L H H H H H H H H H H H H ADV X X X X X X X X L L L L L L H H H H H H WRITE X X X X X X Read Write Read Read Read Read Write Write Read Read Read Read Write Write ISSI OE X X X X X X X X L H L H X X L H L H X X DQ High-Z High-Z High-Z High-Z High-Z Q Q D Q High-Z Q High-Z D D Q High-Z Q High-Z D D (R) PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW H H H H L BWE H L L L X BW1 X H L L X BW2 X H H L X BW3 X H H L X BW4 X H H L X Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 5 IS61SF12832 IS61SF12836 INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 ISSI (R) LINEAR BURST ADDRESS TABLE (MODE = GND) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TBIAS TSTG PD IOUT VIN, VOUT VIN VCC Parameter Temperature Under Bias Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs Voltage on Vcc Supply Relatiive to GND Value Unit -40 to +85 C -55 to +150 C 1.6 W 100 mA -0.5 to VCCQ + 0.3 V -0.5 to VCC + 0.5 V -0.5 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. 6 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 IS61SF12832 IS61SF12836 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V +10%, -5% 3.3V +10%, -5% ISSI (R) DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current GND VIN VCCQ(2) Com. Ind. Test Conditions IOH = -4.0 mA IOL = 8.0 mA Min. 2.4 -- 2.0 -0.3 -2 -5 -2 -5 Max. -- 0.4 VCC + 0.3 0.8 2 5 2 5 Unit V V V V A A GND VOUT VCCQ, OE = VIH Com. Ind. POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol ICC Parameter AC Operating Supply Current Test Conditions Device Selected, All Inputs = VIL or VIH OE = VIH, Vcc = Max. Cycle Time tKC min. Com. Ind. 7.5 Max. 270 -- 8 Max. 250 260 8.5 Max. 230 240 10 Max. 190 200 12 Max. 170 180 Unit mA ISB Standby Current Device Deselected, Com. VCC = Max., Ind. All Inputs = VIH or VIL CLK Cycle Time tKC min. ZZ = VCCQ Com. Clock Running Ind. All Inputs GND + 0.2V or Vcc - 0.2V 50 -- 50 60 50 60 50 60 50 60 mA IZZ Power-down Mode Current 10 -- 10 15 10 15 10 15 10 15 mA Notes: 1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VCC. 2. The MODE pin should be tied to Vcc or GND. It exhibits 10 A maximum leakage current when tied to GND + 0.2V or Vcc - 0.2V. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 7 IS61SF12832 IS61SF12836 CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF ISSI (R) Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 3.3V. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 3.3V 317 ZO = 50 OUTPUT Output Buffer 30 pF 50 1.5V 5 pF Including jig and scope 351 Figure 1 Figure 2 8 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 IS61SF12832 IS61SF12836 READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) 7.5 ISSI Min. Max. -- 8.5 3 3 -- 2 0 2 -- 0 -- 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 117 -- -- -- 7.5 -- -- 3.5 3.5 -- 3.5 -- -- -- -- -- -- -- -- -- -- 8 Min. Max. -- 10 4 4 -- 2 0 2 -- 0 -- 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 100 -- -- -- 8 -- -- 3.5 3.5 -- 3.5 -- -- -- -- -- -- -- -- -- -- 8.5 Min. Max. -- 11 4.5 4.5 -- 2 0 2 -- 0 -- 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 90 -- -- -- 8.5 -- -- 3.5 3.5 -- 3.5 -- -- -- -- -- -- -- -- -- -- 10 Min. Max. -- 15 4.5 4.5 -- 2 0 2 -- 0 -- 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 66 -- -- -- 10 -- -- 3.5 3.5 -- 3.5 -- -- -- -- -- -- -- -- -- -- 12 Min. Max. -- 15 4.5 4.5 -- 2 0 2 -- 0 -- 4 4 4 4 4 1.5 1.5 1.5 1.5 1.5 66 -- -- -- 12 -- -- 3.5 5 -- 3.5 -- -- -- -- -- -- -- -- -- -- (R) Symbol fMAX(3) tKC (3) Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tKH tKL(3) tKQ (3) (1) (1,2) tKQX tKQLZ tOEQ tKQHZ(1,2) (3) (1,2) (1,2) tOELZ tAS(3) tSS(3) tWS tOEHZ (3) (3) tCES tAH tSH tAVS(3) (3) (3) (3) tWH tCEH(3) tAVH (3) Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 3. Tested with load in Figure 1. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 9 IS61SF12832 IS61SF12836 READ/WRITE CYCLE TIMING tKC ISSI tKH tKL (R) CLK tSS tSH ADSP is blocked by CE inactive ADSP tSS tSH ADSC ADV tAS tAH A16-A0 RD1 tWS tWH WR1 RD2 RD3 GW tWS tWH BWE tWS tWH BW4-BW1 tCES tCEH WR1 CE Masks ADSP CE tCES tCEH CE2 and CE2 only sampled with ADSP or ADSC CE2 tCES tCEH Unselected with CE2 CE2 tOEHZ OE tOEQX tKQX DATAOUT High-Z tKQLZ tKQ 1a tKQX tKQHZ 2a 2b 2c 2d tKQHZ DATAIN High-Z tDS 1a tDH Single Read Flow-through Single Write Burst Read Unselected 10 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 IS61SF12832 IS61SF12836 WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC (1) ISSI 7.5 Min. Max. 8.5 3 3 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 Min. Max. 10 4 4 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8.5 Min. Max. 11 4.5 4.5 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 Min. Max. 15 4.5 4.5 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 12 Min. Max. 15 4.5 4.5 4 4 4 4 4 4 1.5 1.5 1.5 1.5 1.5 1.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (R) Parameter Cycle Time Clock High Time Clock Low Time Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Unit tKH(1) tKL(1) tAS tSS (1) (1) tWS(1) tDS (1) (1) tCES tAVS tSH (1) tAH(1) (1) (1) (1) tDH tWH tCEH(1) tAVH(1) Notes: 1. Tested with load in Figure 1. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 11 IS61SF12832 IS61SF12836 WRITE CYCLE TIMING tKC ISSI tKH tKL (R) CLK tSS tSH ADSP is blocked by CE1 inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS ADV tAS tAH tAVH A16-A0 WR1 tWS tWH WR2 WR3 GW tWS tWH BWE tWS tWH tWS tWH BW4-BW1 tCES tCEH WR1 WR2 CE1 Masks ADSP WR3 CE tCES tCEH CE2 and CE3 only sampled with ADSP or ADSC Unselected with CE2 CE2 tCES tCEH CE2 OE DATAOUT High-Z tDS tDH DATAIN High-Z 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d 3a Single Write Burst Write Write Unselected 12 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 IS61SF12832 IS61SF12836 ISSI 7.5 (R) SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC (3) Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Chip Enable Hold Time ZZ Standby ZZ Recovery Min. Max. 8.5 3 3 -- 2 0 2 -- 0 -- 2 2 2 0.5 0.5 0.5 2 2 -- -- -- 7.5 -- -- 3.5 3.5 -- 3.5 -- -- -- -- -- -- -- -- 8 Min. Max. 10 4 4 -- 2 0 2 -- 0 -- 2 2 2 0.5 0.5 0.5 2 2 -- -- -- 8 -- -- 3.5 3.5 -- 3.5 -- -- -- -- -- -- -- -- 8.5 Min. Max. 11 4.5 4.5 -- 2 0 2 -- 0 -- 2 2 2 0.5 0.5 0.5 2 2 -- -- -- 8.5 -- -- 3.5 3.5 -- 3.5 -- -- -- -- -- -- -- -- 10 Min. Max. 15 4.5 4.5 -- 2 0 2 -- 0 -- 2 2 2 0.5 0.5 0.5 2 2 -- -- -- 10 -- -- 3.5 3.5 -- 3.5 -- -- -- -- -- -- -- -- 12 Min. Max. 15 4.5 4.5 -- 2 0 2 -- 0 -- 4 4 4 1.5 1.5 1.5 2 2 -- -- -- 12 -- -- 3.5 5 -- 3.5 -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc tKH(3) tKL(3) tKQ (3) (1) tKQX tKQLZ(1,2) tKQHZ tOEQ tOELZ tAS tSS (3) (3) (3) (1,2) (3) (1,2) tOEHZ(1,2) tCES tAH(3) tSH(3) tCEH tZZS tZZREC (3) Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 3. Tested with load in Figure 1. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 13 IS61SF12832 IS61SF12836 SNOOZE AND RECOVERY CYCLE TIMING tKC ISSI tSH tKH tKL (R) CLK tSS ADSP ADSC ADV tAS tAH A16-A0 RD1 RD2 GW BWE BW4-BW1 tCES tCEH CE tCES tCEH CE2 tCES tCEH CE2 tOEQ tOEHZ OE tOELZ tOEQX DATAOUT High-Z tKQLZ tKQ 1a tKQX tKQHZ DATAIN High-Z tZZS tZZREC ZZ Single Read Snooze with Data Retention Read 14 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 IS61SF12832 IS61SF12836 ORDERING INFORMATION Commercial Range: 0C to +70C Frequency 7.5 8 8.5 10 12 Order Part Number IS61SF12832-7.5TQ IS61SF12832-7.5B IS61SF12832-8TQ IS61SF12832-8B IS61SF12832-8.5TQ IS61SF12832-8.5B IS61SF12832-10TQ IS61SF12832-10B IS61SF12832-12TQ IS61SF12832-12B Package TQFP PBGA TQFP PBGA TQFP PBGA TQFP PBGA TQFP PBGA ISSI (R) Industrial Range: -40C to +85C Frequency 8 8.5 10 12 Order Part Number IS61SF12832-8TQI IS61SF12832-8.5TQI IS61SF12832-10TQI IS61SF12832-12TQI Package TQFP TQFP TQFP TQFP Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 15 IS61SF12832 IS61SF12836 ORDERING INFORMATION Commercial Range: 0C to +70C Frequency 7.5 8 8.5 10 12 Order Part Number IS61SF12836-7.5TQ IS61SF12836-7.5B IS61SF12836-8TQ IS61SF12836-8B IS61SF12836-8.5TQ IS61SF12836-8.5B IS61SF12836-10TQ IS61SF12836-10B IS61SF12836-12TQ IS61SF12836-12B Package TQFP PBGA TQFP PBGA TQFP PBGA TQFP PBGA TQFP PBGA ISSI (R) Industrial Range: -40C to +85C Frequency 8 8.5 10 12 Order Part Number IS61SF12836-8TQI IS61SF12836-8.5TQI IS61SF12836-10TQI IS61SF12836-12TQI Package TQFP TQFP TQFP TQFP ISSI (R) Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com 16 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 |
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